1. Field of the Invention
The present invention relates to a photoelectric converting apparatus and, more particularly, to a photoelectric converting apparatus for reading out signals from photoelectric conversion elements which can accumulate charges which were photoelectrically converted.
2. Related Background Art
Hitherto, there has been known a photoelectric converting apparatus which photoelectrically converts the incident light and accumulates as signal charges and takes out a signal corresponding to the signal charges. As one of the photoelectric converting apparatuses of such a type, there is a photoelectric converting apparatus in which charges are accumulated into a base region of a bipolar transistor and the accumulated charges are amplified and taken out from an emitter.
FIG. 1 is a circuit constructional diagram of such a conventional photoelectric converting apparatus. Sensor circuits of four rows and four columns are shown here as an example.
FIG. 2 is a timing chart for explaining the operation of the above photoelectric converting apparatus.
In FIG. 1, reference numeral 1 denotes a sensor pixel comprising a bipolar transistor Tr, a capacitor C connected to a base of the transistor Tr, and a P type MOS transistor M. Reference numeral 2 denotes an output line which is connected to an emitter of the bipolar transistor Tr of the pixel; 3 indicates an accumulation capacitor to accumulate an output signal; 4 an MOS transistor for switching between the output line 2 and the capacitor 3; 5 an MOS transistor to reset the output line 2; 6 a horizontal output line to output an output signal; 7 an MOS transistor to transfer an accumulation signal of the accumulation capacitor 3 to the horizontal output line 6 from a horizontal shift register HSR in accordance with an output; 8 an MOS transistor to reset the horizontal output line 6; 9 a horizontal drive line to drive the pixels; and 10 an MOS transistor to select the row of the pixels which are driven in accordance with an output from a vertical shift register VSR. V.sub.1, V.sub.2, V.sub.3, and V.sub.4 denote outputs from the vertical shift register VSR; PHS a start pulse of the horizontal shift register HSR; and PH.sub.1 and PH.sub.2 scan pulses of the horizontal shift register HSR. Outputs H.sub.1 and H.sub.3 from the upper horizontal shift register HSR are synchronized with the scan pulse PH.sub.1. Outputs H.sub.2 and H.sub.4 from the lower horizontal shift register HSR are synchronized with the scan pulse PH.sub.2. On the other hand, PT denotes a pulse which is applied to a gate of the MOS transistor 4; PVC a pulse which is applied to a gate of the MOS transistor 5; and PR a drive pulse.
The sensor operation will now be described hereinbelow with reference to FIG. 2.
First, when the output V.sub.1 is set to the high level and the first row of the sensor pixels is selected, the pulse PT is set to the high level and the pulse PVC is set to the low level, thereby setting the output line 2 and the accumulation capacitor 3 into the floating state. The drive pulse PR is set to the high level, thereby reading out the pixels of the first row. The signals of the pixels existing on odd-number designated columns are accumulated into the upper accumulation capacitor 3 and the signals of the pixels existing on even-number designated columns are accumulated into the lower accumulation capacitor 3. The signal is transferred to the upper horizontal output line 6 synchronously with the scan pulse PH.sub.1. The upper horizontal output line 6 is reset synchronously with the scan pulse PH.sub.2. The signal is transferred to the lower horizontal output line 6 synchronously with the scan pulse PH.sub.2. The lower horizontal output line 6 is reset synchronously with the scan pulse PH.sub.1. For the horizontal scan period, the drive pulse PR is set to the low level and the base of the bipolar transistor Tr of each pixel of the first row is set to the earth potential GND. After completion of the horizontal scan, the drive pulse PR is set to the high level, the base potential is set to the positive potential through a capacitive coupling, a forward current flows to the output line 2 fixed to the GND through the MOS transistor 5, so that the base potential decreases to a predetermined level. When the drive pulse PR is set to the middle level, the potential between the emitter and the base of the bipolar transistor Tr of the pixel is reversely biased, so that the accumulation of the photo charges is started. When the output V.sub.1 is set to the low level and the output V.sub.2 is set to the high level and the second row is selected, the similar operation is repeated in the pixels of the second row. Thus, the amplitude signal outputs from the pixels are sequentially output from the upper and lower amplifiers.
However, in the above conventional photoelectric converting apparatus, the output signals which were transferred to the horizontal output line 6 by the capacitive division between the accumulation capacitors 3 and the horizontal output lines 6 must be certainly reset. The resetting operations of the horizontal output lines 6 become an obstacle when realizing a high processing speed. On the other hand, as described in FIGS. 1 and 2, to sequentially take out the signals of the pixels of one row, the horizontal output lines must be divided into the upper and lower sides and the signals must be output. Particularly, in the case where the signals of two rows must be transferred so as to be simultaneously read out as in the case of a color sensor, the signal transferring method by the above conventional photoelectric converting apparatus is difficult. Further, since the signal transfer to the horizontal output lines 6 is executed by the capacitive division, there is a problem such that the signal voltage appearing on the horizontal output line 6 is lower than the signal voltage accumulated in the accumulation capacitor 3.
On the other hand, power sources V.sub.DD and V.sub.SS are always supplied to output amplifiers AMP and electric powers is consumed, so that it is difficult to realize low electric power consumption.
In addition, in the case where a camera of the multi-plate type is constructed by using, for instance, a plurality of photoelectric converting apparatuses of FIG. 1 or in a multi-chip sensor apparatus in which the construction of FIG. 1 is applied to a linear sensor and a plurality of such linear sensors (sensor train) are connected, a variation of offsets of output amplifiers of the chips appears as a level difference of the images and becomes a cause of the deterioration of the picture quality.
On the other hand, pattern wirings to extract clock pulses for driving the chip and output signals are formed on an attached substrate of the multi-chip sensor. There are parasitic capacitances among the wiring patterns, so that the clock pulses to drive the chips are multiplexed to the output signals and become noise. Particularly, in the photoelectric converting apparatus for reading out an original of the A4 size, B4 size, or the like, the parasitic capacitances are very large and the noises is also large. In addition, such noise further increases when the apparatus is driven at a high speed.
In such a sensor, it is difficult to realize high operating speed because of the noise which is by to the parasitic capacitances among the wiring patterns.